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19-5136; Rev 3; 6/10
TION KIT EVALUA BLE ILA AVA
Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
Features
S Comprehensive Programmability and Diagnostics Using I2C Interface S Autoretry Function in Stand-Alone Mode S Drive Capacitive Loads 3nF Differentially, 4nF to Ground S 112dB Signal-to-Noise Ratio S Low 0.002% THD at 4VRMS into 2.7kI Loads S High PSRR (70dB at 1kHz) S High CMRR (80dB at 1kHz) S Low Output Noise (3VRMS), MAX13326 S Excellent Channel-to-Channel Matching S Load-Dump Transient Protection S Protected Output Against Various Short-Circuit Conditions S ESD Protection for 8kV Contact Discharge, 15kV Air Gap S Long-Distance Drive Capability Typically Up to 15m or Greater S Noise-Rejecting Differential Inputs and Outputs S Low-Power Shutdown Mode < 10A S Hardware or Software MUTE Function S 28-Pin TSSOP Package with Exposed Pad
General Description
The MAX13325/MAX13326 dual audio line drivers provide a reliable differential interface between automotive audio components. The devices feature differential inputs and outputs, integrated output diagnostics, and are controlled using an I2C interface or operate in stand-alone mode. The outputs can deliver up to 4VRMS into 100I loads. The MAX13325 buffers analog audio signals for transmission over long cable distances with a fixed gain of 12dB, whereas the MAX13326 provides a 0dB fixed gain. The diagnostics on the outputs report conditions on a per channel basis, including short to GND, short to battery, overcurrent, overtemperature, and excessive offset. The output amplifiers can drive capacitive loads up to 4nF to ground and 3nF differentially. The outputs are protected according to IEC 61000-4-2 Q8kV Contact Discharge, and Q15kV Air Gap. The MAX13325/MAX13326 are specified from -40NC to +105NC and are available in a 28-pin TSSOP package with an exposed pad.
MAX13325/MAX13326
Applications
Automotive Radio and Rear Seat Entertainment Professional Remote Audio Amplifiers
Typical Operating Circuit
VSUP +5V C6 100nF ADD1 ADD0 SDA SCL TO MICROPROCESSOR FLAG SHDN MUTE I2C INTERFACE AND DIGITAL CONTROL BIAS VDD CHARGE PUMP PGND C3 1F VL CP
Ordering Information
PART PINPACKAGE TEMP RANGE -40NC to +105NC -40NC to +105NC GAIN (dB) 12 0
C1 470nF
D2**
* OPTIONAL R1 1kI D1
+12V Q1
C2 1F
CHOLD
CM
MAX13325GUI/V+ 28 TSSOP-EP* MAX13326GUI/V+ 28 TSSOP-EP*
BIAS CSS GND
C4 10F C5 220nF
/V Denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
1nF
C7 2.2F
FROM AUDIO SOURCE
INLP LEFT INLM
OUTLP OUTLM OUTPUT DIAGNOSTIC
ESD PROTECTION
1nF
C8 2.2F C9 2.2F
FROM AUDIO SOURCE
1nF 1nF 1nF
INRP RIGHT
OUTRP OUTRM
C10 2.2F
INRM MAX13325 MAX13326 1nF
*OPTIONAL : NEEDED FOR AUTOMOTIVE LOAD DUMP PROTECTION ONLY **USE D2 WHEN CHARGE PUMP IS OFF AND EXTERNAL SUPPLY IS PROVIDED TO C HOLD
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
ABSOLUTE MAXIMUM RATINGS
VDD to PGND ........................................................-0.3V to +28V CHOLD .................................................................-0.3V to +28V VL to GND ...............................................................-0.3V to +6V GND, PGND ........................................................-0.3V to +0.3V OUT_ to PGND ........................................................ -0.3V to 28V IN_, BIAS to AGND ..................................-0.3V to (VDD + 0.3V) SCL, SDA, ADD0, ADD1, MUTE, SHDN, FLAG to GND ..........................................................-0.3V to +6V OUT_ Short Circuit to PGND or VDD .........................Continuous Short Circuits Between Any OUT_ ............................Continuous Continuous Power Dissipation (TA = +70NC) (multilayer board) 28-Pin TSSOP (derate 27mW/NC above +70NC) .....2162.2mW Junction-to-Ambient Thermal Resistance (BJA) (Note 1) ........................................................................37NC/W Operating Temperature Range ........................ -40NC to +105NC Storage Temperature Range............................ -65NC to +150NC Junction Temperature .....................................................+150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER Transient Supply Voltage (Load Dump) Operating Supply Voltage Range VDD OVLO Threshold VDD UVLO Threshold VL UVLO Threshold Supply Current Logic Supply Current Shutdown Supply Current Turn-On Time (from Shutdown) Turn-On Time (from Mute) Differential Input Resistance Single-Ended Input Impedance Signal-Path Gain (Note 3) Channel-to-Channel Gain Tracking RINDIF RIN AV SYMBOL CONDITIONS Using external nMOS-RTR020N05, 300ms duration 4.5 2.7 Rising edge Falling edge Falling edge TA = +25NC, no load TA = -40NC to +105NC, no load VL = 5V IDD IL MUTE = VL SHDN = VL, CCSS = 220nF Measure across input Each input to ground (MAX13325) Each input to ground (MAX13326) MAX13325 MAX13326 18 15 12 11.8 -0.2 TA = +25NC TA = -40NC to +105NC 1.7 0.5 0.5 < 0.1 220 6 24 20 16 12 0 30 25 20 12.2 +0.2 Q0.4 2 10 18.5 3.3 2.2 19.2 3.5 2.4 39 50 MIN TYP MAX UNITS AMPLIFIER DC CHARACTERISTICS VDDMAX VDD VL VDDOV VDDUV VLUV IDD IL ISHDN 50 18 5.5 V V V V V mA mA mA FA FA ms ms kI kI dB dB
2
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER Differential Mode Output Balance OUT_+ to OUT_- (Note 4) Output Offset Voltage (OUT_+ to OUT_-) BIAS Voltage BIAS Impedance Output-Voltage Swing Differential VOOS VBIAS ZBIAS MUTE = GND, TA = +25NC MUTE = VL, TA = +25NC Relative to VDD IBIAS = Q10FA VDD = 14.4V, VIN = Q14.4V, RL = 1kI VDD = 5.0V, VIN = Q5V, RL = 1kI VDD = 4.5V to 18V Power-Supply Rejection Ratio Common-Mode Rejection Ratio AMPLIFIER AC CHARACTERISTICS VOUT = 4VRMS, RL = 2.7kI Total Harmonic Distortion Plus Noise (Note 5) THD+N VOUT = 4VRMS, RL = 1kI VOUT = 4VRMS, RL = 100I, VDD = 8V VOUT = 7VRMS, RL = 1kI Total Harmonic Distortion Plus Noise at VDD = 5V (Note 5) Capacitive-Load Stability Capacitive-Load Drive Capability No sustained oscillation CLOAD to GND CLOAD differential 112 dB 122 3 2.5 A-weighted, MAX13325 A-weighted, MAX13326 VIN = 1VRMS, 1kHz To achieve soft mute, CCSS = 220nF VIN = 1VRMS, 1kHz KCP KCP Into and out of mute Into and out of shutdown, 1kI 10 3 -110 4 -75 -70 -45 MHz V/Fs FV dB ms dB dBV dBV VOUT = 1VRMS, RL = 2.7kI THD+N VOUT = 1VRMS, RL = 1kI VOUT = 2VRMS, RL = 1kI 0.002 0.004 0.03 0.2 0.01 0.02 0.8 3 4 3 nF nF % % PSRR CMRR VDD = 14.5V, +500mVP-P ripple at 1kHz VDD = 14.5V, +500mVP-P ripple at 10kHz VIN = 1VRMS, 100Hz to 10kHz -48 69 Q12.5 Q4.2 -80 -96 -95 -80 -80 dB dB SYMBOL CONDITIONS MIN TYP -40 Q0.5 Q0.2 50 92 Q10 Q3 52.5 115 MAX UNITS dB mV % kI V
MAX13325/MAX13326
Signal-to-Noise Ratio (Note 5)
SNR
MAX13325, gain = 12dB, VOUT = 4VRMS, A-weighted MAX13326, gain = 0dB, VOUT = 4VRMS, A-weighted
Unity-Gain Bandwidth Output Slew Rate Output-Voltage Noise Crosstalk Mute Time Mute Attenuation Click-and-Pop Level (Note 6) Click-and-Pop Level (Note 6)
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER CHARGE PUMP Charge-Pump Overdrive Voltage, VCHOLD - VDD (Hard Mode) VCHOLD - VDD (Soft Mode) VCPH VDD = 4.5V, ISOURCE = 6.6mA VDD = 18V, ISOURCE = 6.6mA VDD unconnected, ISOURCE = 40FA, VL = 3.3V VL = 5V CPF[1:0] = 00 Charge-Pump Frequency fCP CPOFF = 0 CPF[1:0] = 01 CPF[1:0] = 10 CPF[1:0] = 11 DIAGNOSTICS Output Current Limit Current-Limit Warning Threshold Open-Load Detection Output Offset Detection Thermal Warning Threshold Thermal Shutdown Threshold Thermal Shutdown Hysteresis ESD PROTECTION Air Gap IEC 61000-4-2 Contact Discharge IEC 61000-4-2 HBM OUT_ pins OUT_ pins All pins Q15 Q8 Q2 kV kV kV Valid when muted 10 Q250 135 165 15 Short to GND or battery 580 230 mA mA kI mV NC NC NC 3.2 4.5 2.1 3.9 333 190 426 260 kHz 4.0 5.5 V SYMBOL CONDITIONS MIN TYP MAX UNITS
VCPS
V
4
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
DIGITAL CHARACTERISTICS
(VDD = 14.4V, VL = 3.3V, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER DIGITAL INTERFACE Input-Voltage High Input-Voltage Low Input-Voltage Hysteresis Input Leakage Current Output Low Voltage Output Leakage Current Stand-Alone FLAG Pulse Width Stand-Alone Fault Retry Time I2C TIMING Serial-Clock Frequency Bus Free Time Hold Time SCL Low Time SCL High Time Data Hold Time Data Setup Time Bus Capacitance Receiving Rise Time Receiving Fall Time Transmitting Fall Time STOP Condition Setup Time Pulse Width of Suppressed Spike fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT CB tR tF tF tSU:STO tSP Per bus line SCL, SDA SCL, SDA SDA, VL = 3.6V 20 + 0.1CB 20 + 0.1CB 20 + 0.05CB 0.6 0 50 Between START and STOP conditions Repeated START condition 0 1.3 0.6 1.3 0.6 0 100 400 300 300 250 900 400 kHz Fs Fs Fs Fs ns ns pF ns ns ns Fs ns FLAG, SDA, ISINK = 3mA FLAG, SDA = 5.5V ADD0, ADD1 = GND ADD0, ADD1 = GND 100 500 VINH VINL VL = 2.7V to 5.5V VL = 2.7V to 5.5V 50 Q100 0.4 2 0.75 x VL 0.25 x VL V V mV FA V FA ms ms SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX13325/MAX13326
Note 2: All devices are 100% tested at TA = +25NC. Limits over temperature are guaranteed by design.
(VOUT_ + ) - (VOUT_ - ) 20 x log Note 3: Signal path gain is defined as: . (VIN_ + ) - (VIN _ - ) Note 3: Signal Path Gain is defined as
Note 4: Measured in differential output mode, differential input voltage 4VP-P (for 0dB gain), 1VP-P (for 12dB gain) 1kHz. Common-mode output balance is defined as: 20 x log
( | VOUT_ + ) - ( VOUT_ - ) . ) x 2
_- Common-Mode Output Balance is defined as Note 5: 22Hz to 22kHz measurement bandwidth. Note 6: KCP level is calculated as 20log[(peak voltage during mode transition, no input signal)/1VRMS]. Units are expressed in dBV.
( VOUT_ + ) + ( VOUT
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Typical Operating Characteristics
(VDD = 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)
SHUTDOWN CURRENT vs. TEMPERATURE
MAX13325 toc01
COMMON-MODE REJECTION RATIO vs. FREQUENCY
MAX13325 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
0.009 0.008 0.007 THDN (%) 0.006 0.005 0.004 0.003 0.002 0.001 0 RIGHT CHANNEL 10 100 1k FREQUENCY (Hz) 10k 100k LEFT CHANNEL 1VRMS OUTPUT
MAX13325 toc03 MAX13325 toc09 MAX13325 toc06
0.40 0.35 SHUTDOWN CURRENT (A) 0.30 0.25 0.20 0.15 0.10 0.05 0 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) NO LOAD INPUTS SHORTED VSHDN = 0V
0 -10 -20 -30 CMRR (dB) -40 -50 -60 -70 -80 -90 -100 10 100 1k FREQUENCY (Hz) 10k 1VRMS INPUT 20kHz AES17 FILTER
0.010
100k
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT VOLTAGE
MAX13325 toc04
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
500mVP-P RIPPLE
MAX13325 toc05
CROSSTALK vs. FREQUENCY
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 10 1VRMS INPUT 20kHz AES17 FILTER
0.020 0.018 0.016 0.014 THD+N (%) 0.012 0.010 0.008 0.006 0.004 0.002 0 0 1 2 3 4 5 6 7 8 9 fIN = 1kHz
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120
CROSSTALK (dB)
RIGHT TO LEFT
LEFT TO RIGHT 100 1k FREQUENCY (Hz) 10k 100k
10
10
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT VOLTAGE (VRMS)
MUTE ATTENUATION vs. FREQUENCY
MAX13325 toc07
OUTPUT-NOISE VOLTAGE vs. FREQUENCY
0 -10 -20 -30 -40 -50 -60 -70 -80 90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 FREQUENCY (kHz)
MAX13325 toc08
FFT vs. FREQUENCY
0 -15 -30 -45 FFT (dBV) -60 -75 -90 -105 -120 -135 -150 VOUT = 1VRMS 1kHz
-60 -64 -68 -72 -76 RIGHT CHANNEL -80 10 100 1k FREQUENCY (Hz) 10k LEFT CHANNEL 2VRMS INPUT A-WEIGHTED
OUTPUT-NOISE VOLTAGE (dBV)
MUTE ATTENUATION (dB)
100k
10 12 14 16 18 20
10
100
1k FREQUENCY (Hz)
10k
100k
6
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
Typical Operating Characteristics (continued)
(VDD = 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)
MAX13325/MAX13326
GAIN ERROR vs. TEMPERATURE
MAX13325 toc10
OUTPUT VOLTAGE vs. CHARGE-PUMP OVERDRIVE VOLTAGE
MAX13325 toc12
GAIN ERROR vs. FREQUENCY
0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -0.040 -0.045 -0.050 10 1VRMS OUTPUT
MAX13325 toc12
0.020 0.015 0.010 GAIN ERROR (dB) 0.005 0 -0.005 -0.010 -0.015 -0.020 RIGHT CHANNEL -40 -25 -10 5 20 35 50 65 80 95 LEFT CHANNEL
10.5 10.0 OUTPUT VOLTAGE (V) 9.5 9.0 8.5 8.0 7.5 7.0 0 THDN = 1% fIN = 1kHz VDD = 14.4 RL = 1kI CPOFF = 1
GAIN ERROR (dB)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 (VCHOLD - VDD) (V)
100
1k FREQUENCY (Hz)
10k
100k
TEMPERATURE (C)
OUTPUT-NOISE VOLTAGE vs. FREQUENCY
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0
MAX13325 toc13
GAIN vs. TEMPERATURE
MAX13325 toc14
GAIN ERROR vs. FREQUENCY
0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -0.040 -0.045 -0.050 10 100 MAX13326 (0dB) 1VRMS OUTPUT
MAX13325 toc15
0.20 0.15 0.10 GAIN (dB) 0.05 0 -0.05 -0.10 -0.15 -0.20 RIGHT CHANNEL MAX13326 (0dB) VOUT = 1VRMS LEFT CHANNEL
MAX13326 (0dB)
OUTPUT NOISE VOLTAGE (dBV)
2
4
6 8 10 12 14 16 18 20 FREQUENCY (kHz)
-40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
95
GAIN ERROR (dB)
1k 10k FREQUENCY (Hz)
100k
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Pin Configuration
TOP VIEW
BIAS VL I.C. I.C. INLP INLM VDD INRM INRP 1 2 3 4 5 6 7 8 9 + 28 CSS 27 FLAG 26 CM 25 CP 24 OUTLP 23 OUTLM 22 CHOLD 21 PGND 20 OUTRP 19 OUTRM 18 GND 17 ADD1 16 SDA EP 15 SCL
MAX13325 MAX13326
I.C. 10 I.C. 11 SHDN 12 MUTE 13 ADD0 14
TSSOP
CONNECT TO PGND.
Pin Description
PIN 1 2 3, 4, 10, 11 5 6 7 8 9 12 13 NAME BIAS VL I.C. INLP INLM VDD INRM INRP SHDN MUTE FUNCTION Analog Bias Voltage. Bypass BIAS to GND with a 10FF capacitor. Logic Supply Voltage. Connect VL to a 2.7V to 5V logic supply. Bypass VL to GND with a 0.1FF capacitor. Internally Connected. Leave unconnected. Left Audio Positive Input. Either input of each pair can be used as a single-ended input, with the complementary input bypassed to GND. Left Audio Negative Input. Either input of each pair can be used as a single-ended input, with the complementary input bypassed to GND. Power-Supply Input. Connect VDD to the supply voltage. Bypass VDD to GND through a 1FF capacitor. Right Audio Negative Input. Either input of each pair can be used as a single-ended input, with the complementary input bypassed to GND. Right Audio Positive Input. Either input of each pair can be used as a single-ended input, with the complementary input bypassed to GND. Shutdown Input. Drive SHDN low to power down the device. Mute Input. Drive MUTE low to mute the outputs. The outputs are low impedance in mute.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
Pin Description (continued)
PIN 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -- NAME ADD0 SCL SDA ADD1 GND OUTRM OUTRP PGND CHOLD OUTLM OUTLP CP CM FLAG CSS EP I2C FUNCTION Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses. Connect ADD0 and ADD1 to GND for stand-alone mode. Serial Clock Serial-Data IO I2C Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses. Connect ADD0 and ADD1 to GND for stand-alone mode. Analog Ground. Ground connection for the input bias and gain circuits. Right Audio Negative Output. Each output is current limited. Right Audio Positive Output . Each output is current limited. Power Ground. Ground connection for the output stage drivers. Charge-Pump Output (When Charge Pump is On; CPOFF = 0). When the charge pump is off, provide an external supply through a diode to the CHOLD input. Bypass CHOLD with 1F to PGND. Left Audio Negative Output. Each output is current limited. Left Audio Positive Outputs. Each output is current limited. Charge-Pump Flying Capacitor, Positive Connection Charge-Pump Flying Capacitor, Negative Connection Open-Drain Fault Flag Output. FLAG indicates a fault on any one channel. In stand-alone mode, FLAG is stretched to a typical pulse width of 100ms. Soft-Start Capacitor Connection. CSS is charged/discharged by < 100FA current to get soft mute/ play transition. Bypass to GND through a 220nF capacitor. Exposed Pad. Connect to PGND.
MAX13325/MAX13326
Detailed Description
The MAX13325/MAX13326 audio line drivers are designed to transmit audio data across noisy environments. The differential interface is highly resistant to noise injection from external sources common to automotive applications.
The MAX13325/MAX13326 operate in stand-alone or I2C-compatible mode with diagnostic outputs capable of detecting short to GND or battery, overcurrent, overtemperature, or excessive offset. A short across another audio output signal line is also protected.
Table 1. Register Address Map
ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 REGISTER TYPE Configuration Command Byte General Fault Left-Channel Fault Right-Channel Fault Flag General Mask Left-Channel Mask Right-Channel Mask NAME CONFIG CMD GFAULT LFAULT RFAULT FLAG GMASK LMASK RMASK READ/WRITE Read/Write Read/Write Read Cleared on Read Cleared on Read Read Read/Write Read/Write Read/Write DEFAULT 0x00 0x00 0x00 0x00 0x00 0x04 (12dB) 0x05 (0dB) 0x00 0x00 0x00
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Configuration Register
Table 2. Configuration Register Format
FUNCTION Configuration Register ADDRESS CODE (HEX) 0x00 REGISTER DATA D7 DIAG D6 ENABLE D5 MUTE D4 CPOFF D3 OLDL D2 OLDR D1 CPF1 D0 CPF0 POR STATE (HEX) 0x00
DIAG: Set DIAG to 1 to enable diagnostic mode. Write '0' to disable diagnostic mode. ENABLE: Set ENABLE bit to 1 to enable the device. Write `0' disables the device. Low on the SHDN pin overrides the ENABLE bit. MUTE: Set the MUTE bit to 1 to mute both the output channels. Output is low impedance when in mute. Low on the MUTE pin input overrides the MUTE bit. CPOFF: Set the CPOFF bit to 1 to turn off the charge pump. CHOLD pin must be externally supplied (see the VCPH parameter in the Electrical Characteristics table). Charge pump is enabled when CPOFF = 0. OLDL: Write 1 to the OLDL bit to initiate the open-load detection for the left channel. To run OLDL again, write `0' and `1' again. OLDR: Write 1 to the OLDR bit to initiate the open-load detection for the right channel. To run OLDR again, write `0' and `1' again.
Table 2a. Charge-Pump Frequency Bits
CPF1 0 0 1 1 CPF0 0 1 0 1 FREQUENCY (kHz) 333 190 426 260
CPF[1:0]: Sets the frequency of the charge pump.
Command Byte Register
Table 3. Command Byte Register Format
FUNCTION Command Byte Register ADDRESS CODE (HEX) 0x01 REGISTER DATA D7 RETRYR D6 RETRYL D5 x D4 x D3 x D2 x D1 x D0 x POR STATE (HEX) 0x00
RETRYR: The right-channel power amplifier switches off after a fault condition. Write `1' to turn it back on after the fault condition. RETRYL: The left-channel power amplifier switches off after a fault condition. Write `1' to turn on the left-channel power amplifier after the fault condition.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
General Faults
MAX13325/MAX13326
Table 4. General Fault Register Format
FUNCTION General Fault Register ADDRESS CODE (HEX) 0x02 REGISTER DATA D7 x D6 TWARN D5 TSHDN D4 DUMP D3 x D2 x D1 x D0 x POR STATE (HEX) 0x00
TWARN: The TWARN bit is set to `1' when the temperature warning threshold is reached. TSHDN: The TSHDN is set to `1' when the temperature shutdown threshold is reached. DUMP: The DUMP bit is set to `1' when the VDD voltage exceeds the overvoltage threshold. Set the appropriate mask bit in the GMASK register to detect the general faults. See Table 8.
Left-Channel Faults
Table 5. Left-Channel Fault Register Format
FUNCTION Left-Channel Fault Register ADDRESS CODE (HEX) 0x03 REGISTER DATA D7 SVDDL D6 SGNDL D5 LIMITL D4 x D3 OFFSETL D2 OPENL D1 x D0 x POR STATE (HEX) 0x00
SVDDL: The SVDDL bit is set to `1' when a short to VDD is detected on the left channel. SGNDL: The SGNDL bit is set to `1' when a short to GND is detected on the left channel. LIMITL: The LIMITL bit is set to `1' when the current-limit threshold is tripped for left output. OFFSETL: The OFFSETL bit is set to `1' when excessive offset is detected on the left-channel output. OPENL: The OPENL bit is set to `1' when an open load is detected on the left channel. Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9. When any bit of the LFAULT register is high, the FLAG output is low.
Right-Channel Faults
Table 6. Right-Channel Fault Register Format
FUNCTION Right-Channel Fault Register ADDRESS CODE (HEX) 0x04 REGISTER DATA D7 SVDDR D6 SGNDR D5 LIMITR D4 x D3 OFFSETR D2 OPENR D1 x D0 x POR STATE (HEX) 0x00
SVDDR: The SVDDR bit is set to `1' when a short to VDD is detected on the right channel. SGNDR: The SGNDR bit is set to `1' when a short to GND is detected on the right channel. LIMITR: The LIMITR bit is set to `1' when the current-limit threshold is tripped for right output. OFFSETR: The OFFSETR bit is set to `1' when excessive offset is detected on the right-channel output. OPENR: The OPENR bit is set to `1' when an open load is detected on the right channel. Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10. When any bit of the RFAULT register is high, the FLAG output is pulled low.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
FLAG Register
Table 7. Flag Register Format
FUNCTION FLAG Register ADDRESS CODE (HEX) 0x05 REGISTER DATA D7 FLAG D6 LHIGHZ D5 RHIGHZ D4 OFFSETL D3 OFFSETR D2 ID2 D1 ID1 D0 ID0 POR STATE (HEX) 0x04/0x05
FLAG: FLAG bit is set to `1' when the FLAG output is logic-low. The FLAG bit allows to quickly access the status of the device without using the FLAG output and without having to read all the fault registers. LHIGHZ: The LHIGHZ bit is set to `1' when the left-channel output is high impedance; for example due to a short circuit. RHIGHZ: The RHIGHZ bit is set to `1' when the right-channel output is high impedance; for example due to a short circuit. OFFSETL: The OFFSETL bit is set to `1' when excessive offset is detected on the left-channel output. OFFSETR: The OFFSETR bit is set to `1' when excessive offset is detected on the right-channel output. ID[2:0]: The ID[2:0] bits indicate the device type (12dB = 100 and 0dB = 101).
General Mask Register
Table 8. General Mask Register Format
FUNCTION General Mask Register ADDRESS CODE (HEX) 0x06 REGISTER DATA D7 0 D6 MTWARN D5 MTSHDN D4 MDUMP D3 x D2 x D1 x D0 x POR STATE (HEX) 0x00
MTWARN: Set MTWARN to `1' to enable the TWARN fault detection. See Table 4. MTSHDN: Set MTSHDN to `1' to enable the TSHDN fault detection. See Table 4. MDUMP: Set MDUMP to `1' to enable the DUMP fault detection. See Table 4.
Left-Channel Mask Register
Table 9. Left-Channel Mask Register
FUNCTION Left-Channel Mask Register ADDRESS CODE (HEX) 0x07 REGISTER DATA D7 MSVDDL D6 MSGNDL D5 MLIMITL D4 0 D3 MOFFSETL D2 MOPENL D1 x D0 x POR STATE (HEX) 0x00
MSVDDL: Set MSVDDL to 1 to enable the short to VDD detection on the left channel. MSGNDL: Set MSGNDL to 1 to enable the short to GND detection on the left channel. MLIMITL: Set MLIMITL to 1 to enable overcurrent detection on the left channel. MOFFSETL: Set MOFFSETL to 1 to enable excessive-offset detection on the left-channel output. MOPENL: Set MOPENL to 1 to enable open-load detection on the left channel.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
Right-Channel Mask Register
MAX13325/MAX13326
Table 10. Right-Channel Mask Register
FUNCTION Right-Channel Mask Register ADDRESS CODE (HEX) 0x08 REGISTER DATA D7 MSVDDR D6 MSGNDR D5 MLIMITR D4 0 D3 MOFFSETR D2 MOPENR D1 x D0 x POR STATE (HEX) 0x00
MSVDDR: Set MSVDDR to 1 to enable the short to VDD detection on the right channel. MSGNDR: Set MSGNDR to 1 to enable the short to GND detection on the right channel. MLIMITR: Set MLIMITR to 1 to enable overcurrent detection on the right channel. MOFFSETR: Set MOFFSETR to 1 to enable excessive-offset detection on the right channel. MOPENR: Set MOPENR to 1 to enable open-load detection on the right channel.
When the DIAG bit and the appropriate mask bits are set to 1, the MAX13325/MAX13326 enter diagnostic mode. In this mode, the MAX13325/MAX13326 detect short to GND, short to battery, overcurrent condition, overtemperature condition, excessive offset, and report the diagnosis using the I2C serial interface, FLAG bit, and the FLAG output.
I2C and Stand-Alone Diagnostics
For stand-alone mode, there exists a 500ms stand-alone fault retry function (for autoretry) until the fault goes away. The FLAG output is pulsed to indicate a fault. Output Short to VDD When in diagnostic mode, the MAX13325/MAX13326 detect if any of the differential outputs is shorted to VDD or battery. Upon detection of the short to VDD or battery, the faulted channel is switched off and its output goes into a high-impedance state. The fault is reported using the I2C interface and the FLAG output. See Table 11.
Table 11. Output Short to VDD/Battery Diagnostic
FAULT CONDITION STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. Left-Channel Output Short to VDD SVDDL bit is set in the LFAULT register. See Table 5. Left channel switches off and output goes to high-impedance state. FLAG is asserted low. FLAG bit set. See Table 7. Right-Channel Output Short to VDD SVDDR bit is set in the RFAULT register. See Table 6. Right channel switches off and output goes to high-impedance state. UNMASK In LMASK register, set MSVDDL bit to 1. See Table 9. RECOVERY Cleared on reading the LFAULT register. See Table 5. Note: 500ms autoretry in standalone mode. Output is enabled by setting the RETRYL bit to 1 in the Common Byte register. See Table 3. Cleared on reading the RFAULT register. See Table 6. Note: 500ms autoretry in standalone mode. Output is enabled by setting the RETRYR bit to 1 in the Command Byte register. See Table 3.
Cannot be masked.
In RMASK register, set MSVDDR bit to 1. See Table 10.
Cannot be masked.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Output Short to GND When in diagnostic mode, the MAX13325/MAX13326 detect if any of the differential outputs is shorted to ground. Upon detection of the short to ground, the faulted channel is switched off and its output goes into a high-impedance state. The fault is reported using the I2C interface and the FLAG output. See Table 12. Overtemperature When in diagnostic mode, if the MAX13325/MAX13326 exceed the overtemperature warning or temperature shutdown thresholds the device reports the condition using the I2C interface and the FLAG output. See Table 13.
Table 12. Output Short to GND Diagnostic
FAULT CONDITION STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. Left-Channel Output Short to GND SGNDL bit is set in the LFAULT register. See Table 5. Left channel switches off and output goes to high-impedance state. FLAG is asserted low. FLAG bit set. See Table 7. Right-Channel Output Short to GND SGNDR bit is set in the RFAULT register. See Table 6. Right channel switches off and output goes to high-impedance state. UNMASK In LMASK register, set MSGNDL bit to 1. See Table 9. RECOVERY Cleared on reading the LFAULT register. See Table 5. Note: 500ms autoretry in standalone mode. Output is enabled by setting the RETRYL bit to 1 in the Command Byte register. See Table 3. Cleared on reading the RFAULT register. See Table 6. Note: 500ms autoretry in standalone mode. Output is enabled by setting the RETRYR bit to 1 in the Command Byte register. See Table 3.
Cannot be masked.
In RMASK register, set MSGNDR bit to 1. See Table 10.
Cannot be masked.
Table 13. Overtemperature Diagnostic
FAULT CONDITION Overtemperature Warning STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. TWARN bit is set in the GFAULT register. See Table 4. FLAG is asserted low. FLAG bit set. See Table 7. TSHDN bit is set in the GFAULT Register. See Table 4. Overtemperature Shutdown Left and right channels switch off and output goes to highimpedance state. Cannot be masked. In GMASK register, set MTSHDN bit to 1. See Table 8. UNMASK In GMASK register, set MTWARN bit to 1. See Table 8. RECOVERY Die temperature falls below warning threshold. Cleared on reading the GFAULT register. Die temperature falls below shutdown threshold. Cleared on reading the GFAULT register. Note: 500ms autoretry in standalone mode. Left channel is enabled by setting the RETRYL bit to 1 in the Command Byte register. Right channel is enabled by setting the RETRYR bit to 1 in the Command Byte register. See Table 3.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
Excessive Offset When in diagnostic mode with mute enabled, if there is excessive offset on any output, the MAX13325/ MAX13326 reports the condition through the I2C interface and the FLAG output. See Table 14. Overcurrent When in diagnostic mode, if any of the output pairs is excessively loaded, the MAX13325/MAX13326 issue a warning and report the condition through the I2C interface and the FLAG output. The faulted channel is not switched off. See Table 15. Open Load When in diagnostic mode and the open-load detection is initiated, the selected channel is switched off for 1ms during which the diagnosis is taking place. Upon detecting an open load on any channel, the MAX13325/ MAX13326 report the condition using the I2C interface and the FLAG output. See Table 16. Overvoltage When in diagnostic mode, if the MAX13325/MAX13326 exceed the VDD overvoltage threshold (for example during a load-dump condition), the device reports the condition using the I2C interface and the FLAG output. See Table 17.
MAX13325/MAX13326
Table 14. Excessive Offset Diagnostic
FAULT CONDITION Excessive Output Offset on Left Channel Excessive Output Offset on Right Channel STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. OFFSETL bit is set in the LFAULT register. See Table 5. FLAG is asserted low. FLAG bit set. OFFSETR bit is set in the RFAULT register. See Table 6. UNMASK In the LMASK register, set MOFFSETL bit to 1. See Table 9. In the RMASK register, set MOFFSETR bit to 1. See Table 10. RECOVERY Cleared on reading the LFAULT register.
Cleared on reading the RFAULT register.
Table 15. Overcurrent Diagnostic
FAULT CONDITION Overcurrent on Left Channel STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. LIMITL bit is set in the LFAULT register. See Table 5. FLAG is asserted low. FLAG bit set. See Table 7. LIMITR bit is set in the RFAULT register. See Table 6. UNMASK In the LMASK register, set MLIMITL bit to 1. See Table 9. In the RMASK register, set MLIMITR bit to 1. See Table 10. RECOVERY Load current falls below the current-limit threshold. Cleared on reading the LFAULT register. Load current falls below the current-limit threshold. Cleared on reading the RFAULT register.
Overcurrent on Right Channel
Table 16. Open-Load Diagnostic
FAULT CONDITION Left-Channel Open Load STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. OPENL bit is set in the LFAULT register. See Table 5. FLAG is asserted low. FLAG bit set. See Table 7. OPENR bit is set in the RFAULT register. See Table 6. UNMASK In the LMASK register, set MOPENL bit to 1. See Table 9. In the RMASK register, set MOPENR bit to 1. See Table 10. RECOVERY Cleared on reading the LFAULT register.
Right-Channel Open Load
Cleared on reading the RFAULT register.
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Table 17. Overvoltage Diagnostic
FAULT CONDITION STATUS REPORT FLAG is asserted low. FLAG bit set. See Table 7. DUMP bit is set in the GFAULT register. See Table 4. UNMASK In GMASK register, set MDUMP bit to 1. See Table 8. RECOVERY VDD voltage falls below overvoltage threshold. Cleared on reading the GFAULT register. Note: 500ms autoretry in stand-alone mode.
Overvoltage Shutdown
Left and right channels switch off and output goes to a high-impedance state.
Cannot be masked.
Left channel is enabled by setting the RETRYL bit to 1. Right channel is enabled by setting the RETRYR bit to 1. See Table 3.
Applications Information
Writing to the MAX13325/MAX13326 using I2C requires that first the master sends a START (S) condition followed by the device's I2C address. After the address, the master sends the register address of the register that is to be programmed. The master then ends communication by issuing a STOP (P) condition to relinquish
Serial Interface
control of the bus, or a Repeated START (Sr) condition to communicate to another I2C slave (see Figure 1). Bit Transfer Each SCL rising edge transfers one data bit. The data on SDA must remain stable during the high portion of the SCL clock pulse (see Figure 2). Changes in SDA while SCL is high are read as control signals (see the START and STOP Conditions section). When the serial interface is inactive, SDA and SCL idle high.
SDA tF tLOW tLOW tSU:DAT tF tHD:STA tSP tR tBUF
SCL tHD:STA S tSU:STA Sr tSU:STO P S
tHD:DAT
tHIGH
Figure 1. I2C Timing
SDA SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 2. Bit Transfer 16 _____________________________________________________________________________________
Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic
START and STOP Conditions A master device initiates communication by issuing a START condition, which is a high-to-low transition on SDA with SCL high. A START condition from the master signals the beginning of a transmission to the MAX13325/MAX13326. The master terminates transmission by a STOP condition (see the Acknowledge Bit section). A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 3). The STOP condition frees the bus. If a Repeated START condition is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect slave ID is detected, the device internally disconnects SCL from the
START CONDITION SDA
serial interface until the next START or Repeated START condition, minimizing digital noise and feedthrough. Acknowledge Bit The acknowledge (ACK) bit is a clocked 9th bit that the MAX13325/MAX13326 use to handshake receipt of each byte of data when in write mode. The MAX13325/ MAX13326 pull down SDA during the entire mastergenerated 9th clock pulse if the previous byte is successfully received (see Figure 4). Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event
STOP CONDITION
MAX13325/MAX13326
SCL
Figure 3. START/STOP Conditions
NOT ACKNOWLEDGE S SDA
ACKNOWLEDGE SCL 1 8 9
Figure 4. Acknowledge and Not-Acknowledge Bits
Table 18. Slave Address
ADD1 ADD0 A6 A5 A4 A3 A2 A1 A0 R/W SLAVE ADDRESS READ (HEX) -- 0xC3 0xC5 0xC7 0xC9 0xCB 0xCD 0xCF SLAVE ADDRESS WRITE (HEX) -- 0xC2 0xC4 0xC6 0xC8 0xCA 0xCC 0xCE MODE
GND GND VL VL VL VL SCL SDA
GND VL GND VL SCL SDA VL VL
-- 1 1 1 1 1 1 1
-- 1 1 1 1 1 1 1
-- 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0
-- 0 0 0 1 1 1 1
-- 0 1 1 0 0 1 1
-- 1 0 1 0 1 0 1
-- 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Standalone I2C I2C I2C I2C I2C I2C I2C 17
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
of an unsuccessful data transfer, the bus master may retry communication. The master must pull down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX13325/MAX13326 are in read mode. An acknowledge must be sent by the master after each read byte to allow data transfer to continue. A notacknowledge is sent when the master reads the final byte of data from the MAX13325/MAX13326, followed by a STOP condition. Slave Address The MAX13325/MAX13326 are programmable to one of seven I2C slave addresses. These slave addresses are unique device IDs. Connect ADD_ to GND, VL, SCL, or SDA to set the I2C slave address. The address is defined as the seven most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the MAX13325/MAX13326 to read mode. Set the read/ write bit to 0 to configure the device to write mode. The address is the first byte of information sent after the START condition.
Register Address Map
Single-Byte Write Operation For a single-byte write operation, send the slave address as the first byte followed by the register address and then a single data byte (see Figure 5). Burst Write Operation For a burst write operation, send the slave address as the first byte followed by the register address and then the data bytes (see Figure 6). Single-Byte Read Operation For a single-byte read operation, send the slave address with the read bit set, as the first byte followed by the register address. Then send a Repeated START condition followed by the slave address. After the slave sends the data byte, send a not-acknowledge followed by a STOP condition (see Figure 7). Burst Read Operation For a burst read operation, send the slave address with a write as the first byte followed by the register address. Then send a Repeated START condition followed by the slave address. The slave sends data bytes until a notacknowledge condition is sent (see Figure 8).
S
S7
S6
S5
S4
S3
S2
S1
R/W =0
ACK
C7
C6
C5
C4
C3
C2
C1
C0
ACK
SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 ACK P
REGISTER ADDRESS
DATA 1
Figure 5. A Single-Byte Write Operation
S
S7
S6
S5
S4
S3
S2
S1
R/W =0
ACK
R7
R6
R5
R4
R3
R2
R1
R0
ACK
SLAVE ADDRESS
REGISTER ADDRESS
B7
B6
B5
B4 DATA 1
B3
B2
B1
B0
ACK
B7
B6
B5
B4
B3
B2
B1
B0
ACK
DATA 2
ACK
B7
B6
B5
B4
B3
B2
B1
B0
ACK
P
DATA N
Figure 6. A Burst Write Operation 18 _____________________________________________________________________________________
Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
S S7 S6 S5 S4 S3 S2 S1 R/W =0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK SLAVE ADDRESS R/W =1 REGISTER ADDRESS
Sr
S7
S6
S5
S4
S3
S2
S1
ACK
B7
B6
B5
B4
B3
B2
B1
B0
NACK
P
SLAVE ADDRESS
DATA
Figure 7. A Single-Byte Read Operation
S
S7
S6
S5
S4
S3
S2
S1
R/W =0
ACK
B7
B6
B5
B4
B3
B2
B1
B0
ACK
SLAVE ADDRESS R/W =1
REGISTER ADDRESS
Sr
S7
S6
S5
S4
S3
S2
S1
ACK
B7
B6
B5
B4
B3
B2
B1
B0
ACK
SLAVE ADDRESS
DATA 1
ACK
B7
B6
B5
B4
B3
B2
B1
B0
NACK
P
DATA N
Figure 8. A Burst Read Operation
Charge Pump The MAX13325/MAX13326 charge pump can be disabled depending on application requirements. When charge pump is enabled [CPOFF = 0], please follow the charge-pump capacitor selections. When the charge pump is disabled [CPOFF = 1], the flying capacitor (C1) is not needed. There are internal diodes between VDD/OUT_ to CHOLD, so it is important that CHOLD not be forced below VDD or any of the outputs. A series diode needs to be placed between the external supply (VSUP) and CHOLD. See D2 in the Typical Operating Circuit. Charge-Pump Capacitor Selection Use ceramic capacitors with a low ESR for optimum performance. For optimal performance over the extended temperature range, select capacitors with an X7R dielectric. Table 19 lists suggested manufacturers.
Flying Capacitor (C1) The value of the flying capacitor (see the Typical Operating Circuit) affects the charge pump's load regulation and output resistance. A C1 value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of C1 improves load regulation and reduces the charge-pump output resistance. For optimum performance, use a 470nF capacitor for C1. When the charge pump is disabled [CPOFF = 1], the flying capacitor (C1) is not needed. Hold Capacitor (C2) The hold capacitor value (see the Typical Operating Circuit) and ESR directly affect the ripple at the internal negative rail. Increasing the value of C2 reduces output ripple. Likewise, decreasing the ESR of C2 reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. For optimum performance, use a 1FF capacitor for C2.
FAX 770-436-3030 847-925-0899 847-390-4405 WEBSITE www.murata.com www.t-yuden.com www.component.tdk.com 19
Table 19. Suggested Capacitor Vendors
SUPPLIER Murata Taiyo Yuden TDK PHONE 770-436-1300 800-348-2496 847-803-6100
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Power-Supply Bypass Capacitor (C3) The power-supply bypass capacitor (see the Typical Operating Circuit) lowers the output impedance of the power supply, and reduces the impact of the MAX13325/ MAX13326 charge-pump switching transients. Bypass VDD with C3, the same value as C2, and place it physically close to the VDD and PGND pins. With minimal external components, the MAX13325/ MAX13326 can be protected against automotive loaddump conditions. See the Typical Operating Circuit. nMOSFET (Q1) Q1 should be selected to withstand the full-voltage exposure (BVDSS > 45V). The gate-source turn-on voltage should be chosen to be less than VCPS to ensure initial startup. Using an external nMOS, RTR020N05, 300ms duration component provides 50V load-dump protection. Zener Diode (D1) During short-to-battery condition, OUT_ lifts up CHOLD using an internal diode. In order not to violate the maximum gate-source voltage of Q1, a zener diode of appropriate clamping voltage should be added between the gate and source terminals. Series Resistor (R1) Normally, a series resistor for current limitation is needed during short-to-battery condition. R1 should be chosen according to (18V - VDD(min) - VZENER)/1mA so that no excessive current is being drawn from CHOLD. Proper layout and grounding are essential for optimum performance. Connect the EP and GND together at a single point on the PCB. Ensure ground return resistance is minimized for optimum crosstalk performance.
Load-Dump Protection
Layout and Grounding
Chip Information
PROCESS: BCD
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 28 TSSOP-EP PACKAGE CODE U28E+5 OUTLINE NO. 21-0108 LAND PATTERN NO. 90-0147
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Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic MAX13325/MAX13326
Revision History
REVISION NUMBER 0 1 2 3 REVISION DATE 1/10 3/10 4/10 6/10 Initial release Updated the Typical Operating Circuit Added new register bits to Tables 1, 2, and 7. Revised FLAG Register section and added Table 2a and Charge Pump section. Introduced the MAX13326. Updated the Electrical Characteristics table and added new Typical Operating Characteristics graphs. DESCRIPTION PAGES CHANGED -- 1 1, 4, 7, 8-12, 19, 20 1, 4, 5, 7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
21
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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